1. Technical Field
The present disclosure relates to a method of forming a semiconductor device, and more particularly, to a method of forming a wiring layer of a semiconductor device.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, the size of patterns constituting the semiconductor devices has been gradually reduced. In particular, the size of a contact or via hole formed in an insulating layer (or an interlayer insulating layer) to electrically connect a wiring layer to patterns or a silicon substrate has been reduced.
Moreover, due to the increase of the integration density of semiconductor devices, a plurality of wiring layers are now currently being used. In this regard, the height of an insulating layer (or an interlayer insulating layer) formed between the wiring layers has been increased, thereby also increasing the aspect ratio of a contact or via hole formed in the insulating layer. When a contact or via hole having a large aspect ratio is formed in a thick insulating layer by general photolithography, the contact or via hole may not be correctly formed in a silicon substrate due to photolithography limitations.
For example, when a contact hole is formed in a thick insulating layer between gate patterns, the contact hole may be deeply recessed towards a silicon substrate, or the contact hole may be formed inclined towards the gate patterns. Thus, a contact plug filled in the contact hole can be connected to the gate pattern, thereby causing a short circuit. Even when a contact hole is correctly formed in an insulating layer, a metal layer for a contact plug may not be well filled in a contact hole having a large aspect ratio, which thereby in turn may result in an increase in the contact resistance.
In addition, when a plurality of contact holes are formed between gate patterns formed at small intervals, short circuits can be caused between contact plugs filled in the contact holes due to photolithography limitations and the small intervals between the gate patterns. Moreover, when a wiring layer is misaligned on a contact plug and an interlayer insulating layer, short circuits can be caused between the contact plug filled in a contact hole and the misaligned wiring layer.
Also, when a contact hole is formed in a thick insulating layer between gate patterns in order to form a plurality of semiconductor chips in a silicon wafer at a wafer level, the sizes or shapes of the contact holes formed in a semiconductor chip or in a silicon wafer may not be uniform. In this case, the yield of a semiconductor chip manufacturing process may be significantly reduced, which thereby in turn may increase the manufacturing costs of semiconductor chips.